During the process of mask write or direct write, several factors contribute to induce errors and prevent the achievement of the expected pattern fidelity. Some of these factors are the electron scattering (forward and backward), resist diffusion, resist thickness, etching, flare, fogging, metrology, etc. In order to improve the resolution and reduce the impact of these phenomena, there are several strategies of proximity effect correction (PEC), fogging effect correction (FEC), etching compensation, among others. The strategies are based on a prediction of the impact of each effect of a correction of these by means of dose and/or geometry compensation. Therefore, the quality of the correction depends upon the quality of the models used to predict the phenomena, said models being different from one manufacturing process to another. High precision of the model and the corrections can certainly be obtained, but at a high computation cost.
It has become common knowledge to use a decomposition of the model into two models, a first one to compute the corrections of the electronic proximity effects, and a second one to compute all the other corrections, often called the residual model or the resist model. The parameters of the residual model have to be calculated from the characteristics of the target design, so that the model accurately represents the differences between the various pattern configurations in the design. Space, CD and density normally give a good representation of these differences, but other are sometimes used, such as the exploration variables disclosed by Granik (Y. Granik, N. Cobb, “New Process Models for OPC at sub-90 nm Nodes”, Optical Microlithography XVI, proc. SPIE vol 5040, 2010).
Tools that can be used to calculate representative variables in the residual models are the visibility kernels, such as those disclosed by Sato (S. Sato, K. Ozawa, and F. Uesawa, “Dry-etch proximity function for model-based OPC beyond 65-nm node”, proc. SPIE vol 6155, 2006), or Park (J.-G. Park, S.-W. Kim, S.-B. Shim, S.-S. Suh, and H.-K. Oh, “The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate’, Design for Manufacturability though Design-Process Integration V, proc. SPIE vol 7974, 2011). Also, US patent applications published under no. US2010/269084 and US2011/138343 disclose visibility kernels to scan semiconductor designs.
The methods to implement these methods require the calculation of surface integrals within limits which vary with each part of the design under visibility. Also, the number of calculations is multiplied by the number of variables because CD and Space, and density, notably, each require a full surface integral calculation at all the points of interest.
There is therefore a need of an improvement of the kernel models which greatly alleviates the computation load, while giving an accurate representation of the variables.